CIM_PCIBridge¶

Key properties¶

Local properties¶

uint16 MemoryBase

Base address of the memory supported by the bus. The upper 12 bits of this property specify the address bits, AD[31::20], of a 32-bit memory address. Each of the remaining 20 bits of the address are assumed to be 0.

uint8 IOLimit

End address of the I/O addresses supported by the bus. The upper 4 bits of this property specify the address bits, AD[15::12], of the I/O address. Each of the remaining 12 bits of the I/O address are assumed to be 1.

uint8 IOBase

Base address of I/O addresses supported by the bus. The upper 4 bits of this property specify the address bits, AD[15::12], of the I/O address. Each of the remaining 12 bits of the I/O address are assumed to be 0.

uint16 IOBaseUpper16

Upper 16 bits of the supported I/O base address when 32-bit I/O addressing is used. The lower 16 bits are assumed to be 0.

uint32 PrefetchLimitUpper32

Upper 32 bits of the supported prefetch end address when 64-bit addressing is used. The lower 32 bits are each assumed to be 1.

uint16 BridgeType

The type of bridge. Except for “Host” (value=0) and “PCIe-to-PCI” (value=10), the type of bridge is PCI-to-<value>. For type “Host”, the device is a Host-to-PCI bridge. For type “PCIe-to-PCI”, the device is a PCI Express-to-PCI bridge.

ValueMap	Values
0	Host
1	ISA
2	EISA
3	Micro Channel
4	PCI
5	PCMCIA
6	NuBus
7	CardBus
8	RACEway
9	AGP
10	PCIe
11	PCIe-to-PCI
128	Other
	DMTF Reserved

uint16 SecondaryBusDeviceSelectTiming

The slowest device-select timing for a target device on the secondary bus.

ValueMap	Values
0	Unknown
1	Other
2	Fast
3	Medium
4	Slow
5	DMTF Reserved

uint8 SecondayBusNumber

The number of the PCI bus segment to which the secondary interface of the bridge is connected.

uint16 SecondaryStatusRegister

The contents of the SecondaryStatusRegister of the Bridge. For more information on the contents of this register, refer to the PCI-to-PCI Bridge Architecture Specification.

uint16 PrefetchMemoryBase

Base address of the memory that can be prefetched by the bus. The upper 12 bits of this property specify the address bits, AD[31::20], of a 32-bit memory address. Each of the remaining 20 bits of the address are assumed to be 0.

uint8 PrimaryBusNumber

The number of the PCI bus segment to which the primary interface of the bridge is connected.

uint16 IOLimitUpper16

Upper 16 bits of the supported I/O end address when 32-bit I/O addressing is used. The lower 16 bits are each assumed to be 1.

uint8 SecondaryLatencyTimer

The timeslice for the secondary interface when the bridge is acting as an initiator. A 0 value indicates no requirement.

uint16 PrefetchMemoryLimit

End address of the memory that can be prefetched by the bus. The upper 12 bits of this property specify the address bits, AD[31::20], of a 32-bit memory address. Each of the remaining 20 bits of the address are assumed to be 1.

uint8 SubordinateBusNumber

The number of the highest numbered bus that exists behind the bridge.

uint16 MemoryLimit

End address of the memory supported by the bus. The upper 12 bits of this property specify the address bits, AD[31::20], of a 32-bit memory address. Each of the remaining 20 bits of the address are assumed to be 1.

uint32 PrefetchBaseUpper32

Upper 32 bits of the supported prefetch base address when 64-bit addressing is used. The lower 32 bits are assumed to be 0.

Local methods¶

None

Inherited properties¶

Inherited methods¶